Transformation to and from EBLIF

[emonlux]

I have noticed that there are issues with taking an EBLIF netlist generated by Yosys and using SpyDrNet to transform it into an EDF or Verilog netlist and trying to run the new netlist through Vivado

EDF errors in Vivado

1. Port directions are undefined for GND and VCC
2. Instances are Black Boxes so their contents are not defined

Verilog errors in Vivado

1. Syntax errors for wires and instances

Issues taking an EDF or Verilog netlist and using SpyDrNet to transform it into an EBLIF netlist The error for both the EDF and Verilog netlist is the same and stems from composing the EBLIF netlist

1. KeyError: 'EBLIF.comment'
   • spydrnet/ir/first_class_element.py
   • return self._data.getitem(key) on line 81

[jacobdbrown4]

This is directly related to issue #185