byuccl / spydrnet

A flexible framework for analyzing and transforming FPGA netlists. Official repository.
https://byuccl.github.io/spydrnet
BSD 3-Clause "New" or "Revised" License
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Distinguishing pins in multi-bit ports #196

Open jgoeders opened 1 year ago

jgoeders commented 1 year ago

If I have a multi-bit port, how do I distinguish between the various pins?

I have an 8-bit port called Din:

When I iterate over the pins they all look identical. I would expect the InnerPin to have an index property, but I can't find one.

for pin in port.get_pins():
  print(pin)
<class 'spydrnet.ir.InnerPin'; connected to'<class 'spydrnet.ir.Wire'; Contained by Cable.name 'Din' <class 'spydrnet.ir.Cable'; is_downto: True; is_scalar: False; lower index: 0>>'>
<class 'spydrnet.ir.InnerPin'; connected to'<class 'spydrnet.ir.Wire'; Contained by Cable.name 'Din' <class 'spydrnet.ir.Cable'; is_downto: True; is_scalar: False; lower index: 0>>'>
<class 'spydrnet.ir.InnerPin'; connected to'<class 'spydrnet.ir.Wire'; Contained by Cable.name 'Din' <class 'spydrnet.ir.Cable'; is_downto: True; is_scalar: False; lower index: 0>>'>
<class 'spydrnet.ir.InnerPin'; connected to'<class 'spydrnet.ir.Wire'; Contained by Cable.name 'Din' <class 'spydrnet.ir.Cable'; is_downto: True; is_scalar: False; lower index: 0>>'>
<class 'spydrnet.ir.InnerPin'; connected to'<class 'spydrnet.ir.Wire'; Contained by Cable.name 'Din' <class 'spydrnet.ir.Cable'; is_downto: True; is_scalar: False; lower index: 0>>'>
<class 'spydrnet.ir.InnerPin'; connected to'<class 'spydrnet.ir.Wire'; Contained by Cable.name 'Din' <class 'spydrnet.ir.Cable'; is_downto: True; is_scalar: False; lower index: 0>>'>
<class 'spydrnet.ir.InnerPin'; connected to'<class 'spydrnet.ir.Wire'; Contained by Cable.name 'Din' <class 'spydrnet.ir.Cable'; is_downto: True; is_scalar: False; lower index: 0>>'>
<class 'spydrnet.ir.InnerPin'; connected to'<class 'spydrnet.ir.Wire'; Contained by Cable.name 'Din' <class 'spydrnet.ir.Cable'; is_downto: True; is_scalar: False; lower index: 0>>'>

Am I missing something?

ganeshgore commented 1 year ago

You can get that using port.pins.index(pin) or pin.port.pins.index(pin) (if you don't have the relevant port in the scope) Note: this just returns the unique index number in the list (not guaranteed to match with the Verilog index declaration)

jgoeders commented 1 year ago

Thanks @ganeshgore !!!

@emonlux I'm not seeing this in the documentation anywhere? Am I missing it, or it just not documented yet?

Ultimately the behavior I need is given an Instance, I want to find a given OuterPin by string name and (when needed) integer index. Something like:

Instance.get_pin(name)
Instance.get_pin(name, index)

Now that I know how to get the index for a given pin I can build this information myself into a dictionary. I just thought I would ask if this behavior already exists somewhere...

Thanks!

emonlux commented 1 year ago

Currently, there is no function built in for this. I will look into adding this functionality and documenting it.

Edit: I was unable to get to this before leaving.

jacobdbrown4 commented 1 year ago

OuterPins do not have names, however their ports do. I'm guessing the 'name' in your proposed addition would be the port name and then the index would specify what pin. On the other hand, we can give OuterPins names. Perhaps they could be their port name + "_" + their index.

jacobdbrown4 commented 8 months ago

I have added an index property to InnerPin and OuterPin and updated _str_() to include index and port information.

I have also implemented the following as requested:

Instance.get_pin(name)
Instance.get_pin(name, index)

The name is the name of the port. The default index is 0. If no pin matching the name and index is found, None will be returned.

These updates can be found on the next_release branch.