Closed jgoeders closed 1 year ago
Per https://www.verilog.com/VerilogBNF.html#REF170:
An identifier is any sequence of letters, digits, dollar signs ($), and underscore (_) symbol, except that the first must be a letter or the underscore; the first character may not be a digit or $. Upper and lower case letters are considered to be different. Identifiers may be up to 1024 characters long. Some Verilog-based tools do not recognize identifier characters beyond the 1024th as a significant part of the identifier. Escaped identifiers start with the backslash character (\) and may include any printable ASCII character. An escaped identifier ends with white space. The leading backslash character is not considered to be part of the identifier.
This explicitly states that the backslash it not part of the identifier, but is a bit unclear on the whitespace character.
The escaping characters '\' and ' ' are not part of the name : 'foo' is the same object as '\foo '.
It would be simple to change the verilog parser to remove that space and then re-add it when composing. We already have an option to remove the space but maybe we should make it the default.
@jgoeders I updated the Verilog parser to remove the space in names and the composer to reinsert it during composing. I pushed the change to the next_release branch.
This has been merged into the main branch.
I am finding that instances in my netlist like this one:
end up with an instance name with a space at the end in spydernet. For example, this evaluates to true:
Note that there is a space at the end of the instance name in the netlist file generated by Vivado, and the signal name begins with a backslash, but I still don't think the space should be included.