is_downto flag fix for big-endian bundle declaration

byuccl / spydrnet

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

https://byuccl.github.io/spydrnet

BSD 3-Clause "New" or "Revised" License

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is_downto flag fix for big-endian bundle declaration #222

Closed ganeshgore closed 3 months ago

ganeshgore commented 4 months ago

Currently is_dowto property on cable and port for big-endian declaration only works when Verilog is defined in variant1 format and fails for Variant2 format this PR fixes this.

Variant1

module test_definition(input [0:1] upto);
endmodule

Variant2

module test_definition(upto);
    input [0:1] upto;
endmodule