In Verilog functional simulation the default_nettype directive is added to infer undefined signal nets as wire default_nettype wire or to prevent inferring nettype for undefined wires default_nettype none.
I am adding this token to prevent error while parsing verilog file when this directive exist.
In Verilog functional simulation the default_nettype directive is added to infer undefined signal nets as wire
default_nettype wire
or to prevent inferring nettype for undefined wiresdefault_nettype none
. I am adding this token to prevent error while parsing verilog file when this directive exist.