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byuccl / spydrnet

A flexible framework for analyzing and transforming FPGA netlists. Official repository.
https://byuccl.github.io/spydrnet
BSD 3-Clause "New" or "Revised" License
88 stars 21 forks source link

Make the Intermediate Representation Generic #5

Closed thunder-hammer closed 4 years ago

thunder-hammer commented 4 years ago

The intermediate representation is currently not generic. It is tied to EDIF and is unable to handle even some EDIF datastructures. This needs to be fixed.

Steps to fixing this problem:

--Finalize the Creation API: This will allow us to use the creation API as a generic interface for the parser to avoid any direct modification of the netlist and tying the netlist to the representation

--Finalize the Analysis API: This will allow the composer to rely on the analysis api to preform it's functionality without any direct dependence on the EDIF format

--Ensure robust composer and parser The composer and parser need to not check anything into the IR through the APIs that is file type specific this will ensure that all types can be parsed to and composed from

This issue could be related to other issues that will be tracked independently, feel free to link those issues here so that we can track progress as they are solved.

thunder-hammer commented 4 years ago

This is mostly done for EDIF. closing because #9 is the next step in this.