Convert current EDIF Examples to structural verilog and vhdl using vivado

[andrewmkeller]

We currently have 48 edif netlists in spydrnet/support_files/EDIF_netlists.

Not all of these will necessarily be readable of Vivado, but for those that are, use vivado to convert them to structural verilog, and structural vhdl.

Once these netlists are converted, compress them individually (like we did with EDIF) and add them to spydrnet/support_files/verilog_netlists and vhdl_netlists respectively.

We will use these files to test the parser and composer.

Feel free to ask me if you have any questions about parsing in a netlist in one language to vivado and composing it out in another language. (they likely use Verific as there backend netlist engine which allows them to do this.)

[andrewmkeller]

Michael got most of these converted (42) and added to the branch we were looking at.