If you implement a design for a Zynq device in Vivado (link_design, synth, place, etc.) and then immediately call tincr::write_rscp, an invalid rscp is created.
Specifically, an invalid placement.xdc is created because tincr::parts::is_series7 returns 0 when it should return 1. This happens because get_design returns multiple designs instead of 1 and so then get_parts returns the same part multiple times. Then, the family variable actually becomes a list with multiple "zynq" entries. This unexpected output causes tincr::parts::is_series7 to return 0 instead of 1. The placement.xdc relies on knowing whether or not the design is for a Series 7 device or not.
This problem doesn't occur if you first save a DCP, open it, and then call tincr::write_rscp (only one design is returned by get_design if you use the saved DCP).
This can easily be fixed, probably by just checking if any of the detected families are zynq. But I have also noticed some other strange behaviors that occur if you do not first save and open a DCP. For example, trying to write a bitstream will result in Vivado telling you that the design hasn't been implemented yet. But once you save and open a DCP, it works fine.
If I recall correctly, these issues might not exist in newer versions of Vivado (newer than 2016.2).
If you implement a design for a Zynq device in Vivado (link_design, synth, place, etc.) and then immediately call
tincr::write_rscp, an invalid rscp is created.Specifically, an invalid placement.xdc is created because
tincr::parts::is_series7returns 0 when it should return 1. This happens because get_design returns multiple designs instead of 1 and so then get_parts returns the same part multiple times. Then, the family variable actually becomes a list with multiple "zynq" entries. This unexpected output causestincr::parts::is_series7to return 0 instead of 1. The placement.xdc relies on knowing whether or not the design is for a Series 7 device or not.This problem doesn't occur if you first save a DCP, open it, and then call
tincr::write_rscp(only one design is returned by get_design if you use the saved DCP).This can easily be fixed, probably by just checking if any of the detected families are zynq. But I have also noticed some other strange behaviors that occur if you do not first save and open a DCP. For example, trying to write a bitstream will result in Vivado telling you that the design hasn't been implemented yet. But once you save and open a DCP, it works fine.
If I recall correctly, these issues might not exist in newer versions of Vivado (newer than 2016.2).