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byuccl / tincr

A Tcl-based CAD Tool Framework for Xilinx's Vivado Design Suite
GNU General Public License v2.0
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Component files in cache directory #93

Closed ZirconfleX closed 5 years ago

ZirconfleX commented 5 years ago

Hi,

I'm a complete newbie with tincr, just starting to find may way around in directories and files. I do have a question on the FPGA family files in the cache directory. Should there not be directories for Zynq-1000 and Zynq Ultrascale+ parts? Why has the virtexuplus directory only primitive_defs for VCC and GND?

I've seen the issues 3 and 13 but those give no answer.

DallonTG commented 5 years ago

Sorry for the slow response on this!

Originally we believed that all primitive definitions were the same within a family of devices. However, we discovered this wasn't the case with the ZYNQ FPGAs. In the case of ZYNQ, we discovered two different groups of primitive defs:

Group 1: xa7z010clg400-1I_ise_full.xdlrc xa7z020clg400-1I_ise_full.xdlrc xq7z020cl400-1Q_ise_full.xdlrc xc7z010clg400-1_ise_full.xdlrc xc7z020clg400-2_ise_full.xdlrc xa7z010clg225-1I_ise_full.xdlrc xa7z010clg484-1I_ise_full.xdlrc

Group 2: xq7z045rf676-2I_ise_full.xdlrc xc7z030fbg676-3_ise_full.xdlrc xc7z045fbg676-3_ise_full.xdlrc xc7z100ffg900-2_ise_full.xdlr xq7z030rf676-2I_ise_full.xdlrc xq7z030rb484-2I_ise_full.xdlrc

Basically, the bigger FPGAs (in group 2) seem to have site routethroughs not present in the smaller FPGAs (group 1). We generated these primitive defs using Xilinx ISE and I have added directories for Zynq with #94 , so you should be able to create XDLRCs for ZYNQs now.

The newer devices, such as the Zynq Ultrascale+ and virtexu+ parts are harder to create primitive definitions for. We have not yet completed creating primitive definitions for these parts, which is why the directories are missing/incomplete. "Partial" primitive definitions can be created with Tincr, but they have to be manually completed with the VSRT tool. Please see the RapidSmith2 Technical Report, Section 10.2 for more details. If you go through this process we will support you and answer your questions along the way However, we aren't currently planning on generating the primitive definitions ourselves.

Please feel free to re-open the issue if you have additional, related problems.

ZirconfleX commented 5 years ago

Hi,

I think that a lot more of this work is heading in your direction with the new Versal FPGA's arriving soon.

Regards,

Marc