cache flush and invalid

[y00281931]

copied from linux-4.9.y/arch/csky/mm/cache.c

define FLUSH_MAX PAGE_SIZE

void cache_op_range( unsigned int start, unsigned int end, unsigned int value, unsigned int l2) { unsigned long i, flags; unsigned int val = value | CACHE_CLR | CACHE_OMS;

if (unlikely((end - start) >= FLUSH_MAX) ||
    unlikely(start < PAGE_OFFSET) ||
    unlikely(start >= V3GB_OFFSET)) {
    cache_op_all(value, l2);
    return;
}

why flush all if (end - start) >= FLUSH_MAX?

[guoren83]

This is first generation cache hw mechanism, the flush operation is expensive by itself.

Ref: mm/cachev2.c, we've improved it.

[y00281931]

config CPU_CK860 bool "C-SKY CPU 860" select CPU_HAS_TLBI select CPU_HAS_CACHEV2 select CPU_HAS_LDSTEX select CPU_HAS_FPUV2

It seems that cachev2.c is only for CK860. Does it mean that cache flush is also done at high expense in CK810.

[guoren83]

On Mon, Sep 23, 2019 at 2:52 PM y00281931 notifications@github.com wrote:

config CPU_CK860 bool "C-SKY CPU 860" select CPU_HAS_TLBI select CPU_HAS_CACHEV2 select CPU_HAS_LDSTEX select CPU_HAS_FPUV2

It seems that cachev2.c is only for CK860. Does it mean that cache flush is also done at high expense in CK810.

v1 cache flush is more expensive than v2.

Next we'll let 810 could select CPU_HAS_CACHEV2, but may be put it into dts is better.

-- Best Regards Guo Ren

ML: https://lore.kernel.org/linux-csky/

[y00281931]

So cache is v2 in CK810 hardware, but cache operations in kernel is to be updated. Could you please tell me when it will be available?

[guoren83]

On Tue, Sep 24, 2019 at 11:32 AM y00281931 notifications@github.com wrote:

So cache is v2 in CK810 hardware, but cache operations in kernel is to be updated. Could you please tell me when it will be available?

No, ck810 could select v1 or v2 cache mechanism in linux and that depends on your hardware.

-- Best Regards Guo Ren

ML: https://lore.kernel.org/linux-csky/

[y00281931]

Okay. From the function dcache_inv_range, it is not easy for me to find hw cache version out.

void dcache_inv_range(unsigned long start, unsigned long end) { unsigned long i = start & ~(L1_CACHE_BYTES - 1);

for (; i < end; i += L1_CACHE_BYTES) asm volatile("dcache.civa %0\n"::"r"(i):"memory"); sync_is(); }

dcache.civa may be a pseudo instruction which sets CPU control registers. Which registers are they? Or, can I get cache version in register CPUIDRR?

[guoren83]

On Tue, Sep 24, 2019 at 4:33 PM y00281931 notifications@github.com wrote:

Okay. From the function dcache_inv_range, it is not easy for me to find hw cache version out.

void dcache_inv_range(unsigned long start, unsigned long end) { unsigned long i = start & ~(L1_CACHE_BYTES - 1);

for (; i < end; i += L1_CACHE_BYTES) asm volatile("dcache.civa %0\n"::"r"(i):"memory"); sync_is(); }

dcache.civa may be a pseudo instruction which sets CPU control registers. Which registers are they?

No, they are real.

Or, can I get cache version in register CPUIDRR?

I prefer dts :)

-- Best Regards Guo Ren

ML: https://lore.kernel.org/linux-csky/

[y00281931]

So, if the instruction dcache.civa can be executed, the cache hardware must be v2. Is it right?

"No, ck810 could select v1 or v2 cache mechanism in linux and that depends on your hardware." "I prefer dts :)"

I want to check if the hw cache version is v2 or not for the hardware in my hands.

[guoren83]

cat /proc/cpuinfo

On Wed, Sep 25, 2019, 11:58 y00281931 notifications@github.com wrote:

So, if the instruction dcache.civa can be executed, the cache hardware must be v2. Is it right?

"No, ck810 could select v1 or v2 cache mechanism in linux and that depends on your hardware." "I prefer dts :)"

I want to check if the hw cache version is v2 or not for the hardware in my hands.

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