calyxir / calyx

Intermediate Language (IL) for Hardware Accelerator Generators
https://calyxir.org
MIT License
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Sync dot product #1185

Closed paili0628 closed 1 year ago

rachitnigam commented 1 year ago

@paili0628 can you also change the test input so there are zeros in the middle as well? Currently the vectors are all "dense" in their representation and do not have any sparsity in the middle

paili0628 commented 1 year ago

I am not sure why we need sparsity in the middle if we use index-value representation, but take a look, is this what you meant? @rachitnigam

rachitnigam commented 1 year ago

Ah, I didn't realize it was a sparse format. Can you rename the memories to reflect which one is the "index" memory and which one is the "data memory"?

rachitnigam commented 1 year ago

Merge after making those changes!

paili0628 commented 1 year ago

There is no single vector storing index memory or data memory. Both vectors are represented as such: a non-zero value follows its index.

paili0628 commented 1 year ago

I also gave a description of vector representation in the comment at the top.

rachitnigam commented 1 year ago

Sounds good! LGTM!

rachitnigam commented 1 year ago

Oh, can you add a reference from the sync doc to this file as an example of a more complex design that uses @sync?

paili0628 commented 1 year ago

Should this be done after we push our changes onto the main branch? I tried relative path, the link just doesn't work when I tired running on local host.

rachitnigam commented 1 year ago

Ah, I see what you're saying. You could try to concot the correct link by looking at the links github generates for the other files in that directory or open another PR after this one.

rachitnigam commented 1 year ago

@paili0628 is this ready to be merged?

paili0628 commented 1 year ago

Yes.