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calyxir / calyx

Intermediate Language (IL) for Hardware Accelerator Generators
https://calyxir.org
MIT License
450 stars 44 forks source link

Fix pipelined_mult frequency for Vivado #2006

Closed andrewb1999 closed 1 month ago

andrewb1999 commented 1 month ago

For some unknown reason Vivado decides to do DSP inference before retiming so this change actually matters (what a great and stable piece of software). I've tried a lot of combinations of synthesis options and I can't get it to retime the multipliers correctly. This change increases the max frequency from 300 MHz to nearly 500 MHz.

EclecticGriffin commented 1 month ago

what a cool and fun piece of software

rachitnigam commented 1 month ago

Looks like there are no changes to the timing of the module! Annoying that we have to pattern match. LGTM!

andrewb1999 commented 1 month ago

Looks like there are no changes to the timing of the module! Annoying that we have to pattern match. LGTM!

Yep it shouldn't (and doesn't from my testing) impact timing. All I did was push one register before the multiplier. Before this change the module worked like ins -> mult -> reg -> reg -> reg -> reg -> out it now works like ins -> reg -> mult -> reg -> reg -> reg -> out. Both versions will take 4 cycles to produce an output and have an II of 1.