Open ayakayorihiro opened 3 weeks ago
Thanks for opening this @ayakayorihiro! Could you add the "Tracker" label to this issue?
Thanks @rachitnigam ! Just added the tracker label, will keep in mind for next time :)
- Remove assumption that each cycle takes 10ms (have a counter mechanism of how many cycles passed between X ms and Y ms)
For synchronous designs like the ones Calyx produces I generally recommend sampling signals on a rising or falling clock edge (depending on how the testbench works). That way you stay independent of the actual timing. Here is how I find the sample point in a rust implementation: https://github.com/ekiwi/rtl-repair/blob/71e1afc0b9a2327d008b46acd415cf3f0343a938/scripts/osdd/src/main.rs#L113
Similar thing but with the vcdvcd
library in python:
https://github.com/ekiwi/rtl-repair/blob/861e244c599e682efe5dbd8e3295c3b8e3590a34/scripts/calc_osdd.py#L215
https://github.com/ekiwi/rtl-repair/blob/861e244c599e682efe5dbd8e3295c3b8e3590a34/scripts/calc_osdd.py#L195
Thanks @ekiwi ! I'll take a stab following your work with the vcdvcd
library :)
This issue lists out first steps for profiling! (Mostly so I can organize my TODOs.) Will update as I move along.
First Pass: Cycle-level performance info at the Calyx level
FSMStateInfo
when processing enables.language-tutorial-iterate
, the individual TDCC FSMs overwrite each other)