calyxir / calyx

Intermediate Language (IL) for Hardware Accelerator Generators
https://calyxir.org
MIT License
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Probably fix #2016: Sort ports when compiling refs #2018

Closed sampsyo closed 3 weeks ago

sampsyo commented 3 weeks ago

This is a really tiny change to force an ordering on the "inlined" ports when compiling ref cells, to address #2016.

Recall that compiling ref cells (which happens in compile-invoke, despite the name) involves creating ports in the "host" component to mirror those in the ref cell it contains. Those ports are created by an ir::Rewriter, which produces a HashMap, which is of course nondeterministic. The strategy here is to just take those randomly-ordered ports and sort them before we add them to the "host" component, yielding deterministic IR from this pass.

I don't know if this is the best way, but it is at least a way.

rachitnigam commented 3 weeks ago

We generally use LinkedHashMap instead of sorting for these cases in other parts of the code base. Unclear which solution is better overall since we don't care about insertion order; just a stable order

rachitnigam commented 3 weeks ago

This is a fine fix for now. Merging!