Queues: Tidy the FIFO and PIFO

[anshumanmohan]

Just a little tidying in the FIFO and the PIFO.

1. I take the length of the queue as a Python-level argument instead of always leaving it to a constant.
2. I used to zero out the ans cell when the queue component had an error; this turned out not to be necessary.
3. In the FIFO component, I have unified the control logic for popping and peeking, with popping requiring a couple additional steps. This means the control logic splits into two arms (pop/peek, and push, with an if-check in the pop/peek arm) instead of splitting into three arms (pop, peek, push). The same is possible in the PIFO, but I have left the three arms for simplicity.

My original goal was actually to turn ans and err, which are currently registers passed to the queue component by reference, into output ports. I've decided that change is a little too much trouble for now.

I have a new silly thought, which I'll flesh out in a comment below.

[anshumanmohan]

A silly thought re: FIFO's max length

At present, the FIFO is internally just 1-d memory that I treat as a circular buffer. Two registers, read and write, mark which cell of the memory should next be read from or written to. The registers are incremented as needed, and, when they equal the maximum length of the queue, they are zeroed out to simulate a wraparound.

Perhaps super silly, but I was wondering how we'd feel about requiring the queue's maximum length to be a power of 2. Then we'd be able to simply keep incrementing these registers forever, trusting actual overflow to do the zeroing-out for us. We'd save a couple of equality-checking cells and the wiring needed to run those checks and potentially zero the registers.

[anshumanmohan]

Update: the silly thought is its own PR, #2028