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cambridgehackers / connectal

Connectal is a framework for software-driven hardware development.
MIT License
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axiddr3, dma, vsim, generate_constraint.py #114

Closed hanw closed 8 years ago

hanw commented 8 years ago

@jameyhicks These changes has been sitting on our tree for a little while. May be time to merge in.

It contains a fix in 4c7bfdb from @kslee for a corner case in DMA.

One piece I am not sure about is the change in 7ebdbd2 to Makefile.connectal.build, I needed it to compile a cpp file to simulate associative memory (using unordered_map in c++).

/// This is obsolete /// Also, another change in 7ebdbd2 to allow me to simulate xilinx 10G mac, but the change seems like a hack now. I can remove the change if you don't like it.

kslee commented 8 years ago

4c7bfdb Altera Avalon adds some redundant data to Mem completion packets. As a result, wordCount should be the length of the data following the completion packet, although the completion packet also contains the first 4 bytes of it.

hanw commented 8 years ago

Can we merge now? anything else I should fix in this pull request?