search

cambridgehackers / connectal

Connectal is a framework for software-driven hardware development.
MIT License
161 stars 46 forks source link

Support Third-Party simulate (verify on ncverilog and vcs only) #121

Closed chenm001 closed 4 years ago

chenm001 commented 8 years ago

This feature enable full system debug in verilog environment with fsdb waveform database Usage example: make build.bluesim.vcs

jameyhicks commented 8 years ago

travis-ci fails because the LM_LICENSE_FILE is encrypted and not available to branches or pull requests so that check can be ignored.

jameyhicks commented 8 years ago

I added boardinfo for vcs and ncverilog boards.

chenm001 commented 8 years ago

make build.vcs ...... make[1]: *\ No rule to make target 'vcssim', needed by 'bits'.

jameyhicks commented 8 years ago

In your pull request, please add a rule to build vcssim.

On Thu, Jun 9, 2016 at 4:43 PM Min Chen notifications@github.com wrote:

make build.vcs ...... make[1]: *\ No rule to make target 'vcssim', needed by 'bits'.

— You are receiving this because you commented.

Reply to this email directly, view it on GitHub https://github.com/cambridgehackers/connectal/pull/121#issuecomment-225020238, or mute the thread https://github.com/notifications/unsubscribe/ACU3sykpiKTc4hv6ej9FHo15JSpb_cgMks5qKHrcgaJpZM4IxdTV .

chenm001 commented 8 years ago

I don't add new target because, I want not use SVDPI, because DPI interface depends on simulate and its version, the BDPI is more compatible on simulate/debug environment. But current code support BDPI on board_bluesim only, so I use sub-target based on bluesim.

jameyhicks commented 8 years ago

In my experience BDPI also depends on the simulator. Xilinx xsim does not support Verilog VPI, so BDPI does not work with that simulator. If you generate verilog from BSV with BDPI, then I have seen it generate the VPI headers. I do not think you have to use bsc to run the verilog simulator.

However, the way connectal applications talk to connectal hardware does require SystemVerilog DPI. I assume ncverilog and vcs support this?

On Wed, Jun 15, 2016 at 5:42 PM Min Chen notifications@github.com wrote:

I don't add new target because, I want not use SVDPI, because DPI interface depends on simulate and its version, the BDPI is more compatible on simulate/debug environment. But current code support BDPI on board_bluesim only, so I use sub-target based on bluesim.

— You are receiving this because you commented.

Reply to this email directly, view it on GitHub https://github.com/cambridgehackers/connectal/pull/121#issuecomment-226329075, or mute the thread https://github.com/notifications/unsubscribe/ACU3sx7aRnMhfEvaOFHLn6MdZHd4MWBcks5qMHHKgaJpZM4IxdTV .

chenm001 commented 8 years ago

so I use format build.bluesim.vcs, it may generate DPI wrapper on bsc supported simulate.

btw: I know we may get VPI header files, but BDPI control by Board_bluesim, and bsc can't handle `if

jameyhicks commented 8 years ago

I don't want to use board name bluesim.vcs. If we need additional defines to work around limitations of SystemVerilog preprocessors, we can add them to boardinfo/vcs.json etc.

On Wed, Jun 15, 2016 at 6:05 PM Min Chen notifications@github.com wrote:

so I use format build.bluesim.vcs, it may generate DPI wrapper on bsc supported simulate.

btw: I know we may get VPI header files, but BDPI control by Board_bluesim, and bsc can't handle `if

— You are receiving this because you commented.

Reply to this email directly, view it on GitHub https://github.com/cambridgehackers/connectal/pull/121#issuecomment-226334297, or mute the thread https://github.com/notifications/unsubscribe/ACU3s6DlZSijDqZ6MoKiFsBIdNMaNnYsks5qMHc9gaJpZM4IxdTV .

chenm001 commented 8 years ago

it is not board name, it means based on bluesim with extra vsim option vcs