Closed jameyhicks-cmt closed 2 years ago
Using DataBusWidth=256 with this branch compiled and synthesized for the vcu118 target, and worked in simulation for the verilator target.
I am yet to push the synthesized version onto the FPGA and will confirm later that it works in hardware, but so far so good!
@RadhikaG thank you for testing! I do not currently have access to any vcu118s.
Rebased https://github.com/xushuotao/connectal branch master and imported XilinxVirtex7PCIE.bsv