jameyhicks
commented
9 years ago 1) There are both Xilinx and Altera examples included in fpgamake, but they were not documented. Both depend on BSV. If I am allowed to check in the BSV Verilog libraries, I'll do so.
Otherwise, I'll find a small Verilog example to add. I should do this anyway, to make a simpler example. Pull requests are welcome, of course.
2) ?
3) Added dependence on buildcache to the documentation, and to the debian/control file for the packages.
4) Updated README.md
These changes made in release v15.04.1.
aolofsson
This is what I did and what I get for errors so far:
1.) Downloaded a tutorial. (would be great if there was package in the fpgamake repo, or perhaps you could use the Parallella project once ready?)
https://secure.xilinx.com/webreg/clickthrough.do?cid=363329&cancellink=http%3A%2F%2Fwww.xilinx.com%2Fsupport%2Fdocumentation%2Findex.htm
2.) ./fpgamake --board='noboard' --part='xc7k70tfbg676-2' -b top.bit -o fpgamake.mk -t sys_integration_top --constraints=/home/aolofsson/Work_others/fpgamake/ug939-design-files/lab_4/sources/Constraints/top.xdc /home/aolofsson/Work_others/fpgamake/ug939-design-files/lab_4/sources/HDL
3.) make -f fpgamake.mk parallella:~/Work_others/fpgamake> make -f fpgamake.mk fpgamake.mk Synth/sys_integration_top/sys_integration_top-synth.dcp /bin/sh: /home/aolofsson/Work_others/buildcache/buildcache: No such file or directory make: *\ [Synth/sys_integration_top/sys_integration_top-synth.dcp] Error 127
4.) realized that I had to clone your 'buildcache' repo parallel to the fpgamake? Did I miss this in the help?
5.) Working my way through example now....