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cambridgehackers / fpgamake

Generates Makefiles to synthesize, place, and route verilog using Vivado
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Add file path checker to flow (feature request) #12

Closed aolofsson closed 9 years ago

aolofsson commented 9 years ago

I put in the wrong argument for "-t" so the file top.v didn't exist. That gave me the following message. Would be nice if flow gave a clearer hint as to the where the error might be (for idiots like me:-))

File "./fpgamake", line 498, in process_modules() File "./fpgamake", line 227, in process_modules shutil.copyfile(vpath, os.path.join(synthdir, vfile)) File "/usr/lib/python2.7/shutil.py", line 68, in copyfile if _samefile(src, dst): File "/usr/lib/python2.7/shutil.py", line 58, in _samefile return os.path.samefile(src, dst) File "/usr/lib/python2.7/posixpath.py", line 162, in samefile s1 = os.stat(f1) TypeError: coercing to Unicode: need string or buffer, NoneType found

aolofsson commented 9 years ago

Same thing goes for the xdc file..you don't want to go through synthesis only to find out that the path was wrong (doh!)

jameyhicks commented 9 years ago

I added checkers for the following file types: verilog, xci, constraints, and floorplan. I think I might have missed a couple.

jameyhicks commented 9 years ago

I think I would like to make sure that all the modules referenced in the verilog are present in the libraries or cores, but I'll need a list of the built-in cores, but that would be another feature.