cambridgehackers / fpgamake

Generates Makefiles to synthesize, place, and route verilog using Vivado
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FPGA program not done due to DCI matching failure #18

Closed chanwooc closed 8 years ago

chanwooc commented 8 years ago

If DCI matching fails, FPGA is not programmed properly by default. Setting "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait makes FPGA programmed successfully without checking DCI matching.

jameyhicks commented 8 years ago

This is really helpful. All the keywords in one place. :)