search

cambridgehackers / fpgamake

Generates Makefiles to synthesize, place, and route verilog using Vivado
92 stars 24 forks source link

Example project misses 'bsc' command #22

Open ranzbak opened 4 years ago

ranzbak commented 4 years ago

I'm running Mint Linux 19.2, and I used the apt get method to install the fpgamake software on my machine. One of the first steps I am trying is to build an example project, but I'm not able to, it seems like the 'bsc' command is missing on my machine? The documentation doesn't mention anything about bsc. Please let me know if more information is needed.

Output from: make

/usr/bin/time bsc -u -verilog -elab -reset-prefix RST_P -D BSV_POSITIVE_RESET \
-p +:bsv \
-bdir /home/paul/work/fpga/fpgamake/fpgamake/examples/uart_kc705/kc705/bo -vdir verilog -info-dir /home/paul/work/fpga/fpgamake/fpgamake/examples/uart_kc705/kc705/info -p :+ -no-show-method-conf \
-show-schedule -show-compiles -aggressive-conditions -keep-fires -no-inline-rwire   \
-remove-dollar -show-range-conflict -scheduler-effort 500 bsv/DutTop.bsv
/usr/bin/time: cannot run bsc: No such file or directory
Command exited with non-zero status 127
0.00user 0.00system 0:00.00elapsed ?%CPU (0avgtext+0avgdata 1120maxresident)k
0inputs+0outputs (0major+27minor)pagefaults 0swaps
Makefile:17: recipe for target 'verilog/mkDutTop.v' failed
make: *** [verilog/mkDutTop.v] Error 127
jameyhicks commented 4 years ago

bsc is the Bluespec System Verilog compiler from bluespec.com. It is available for free for academic use. The goal of splitting fpgamake out of connectal was to make it independent of BSV, so it was an error on my part to add an example that depends on bsc.

The led_sw example does not depend on BSV. I could also commit the Verilog generated by BSV for the kc705 example if that would be helpful.