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cambridgehackers / fpgamake

Generates Makefiles to synthesize, place, and route verilog using Vivado
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Support "-f" source file specification like verilator and icarus #9

Open aolofsson opened 9 years ago

aolofsson commented 9 years ago

One thing that would help me (and possibly others) get up to spee quickly would be if I could use the same source command file that I use for icarus and verilator (arguably the two most popular open source simulators) to feed the fpgamake tool. The argument would typically be "-f my.cmd".

During evaluation, either read the file list as specified in command file or read the constants first. (the constants parts has given me problems in chip and synthesis tools).

An example of the content of the command file can be seen here.

../../constants/hdl/simulation_constants.v ../../elink/hdl/elink_regmap.v dv_elink_tb.v -y . -y ../../elink/hdl -y ../../stubs/hdl -y ../../common/hdl -y ../../memory/hdl -y ../../embox/hdl -y ../../emmu/hdl

jameyhicks commented 9 years ago

This is a good idea -- I will implement it.

jameyhicks commented 9 years ago

What is the difference between verilator -f foo.vc and verilator -F foo.vc? The help message says the first one is handled "relatively".