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cambridgehackers
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open-src-cvc
Mirror of tachyon-da cvc Verilog simulator
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ld multiple definition error
#11
sfmth
opened
11 months ago
0
Is the delay from the output of the cell to the output port of the chip specified by INTERCONNECT ?
#10
takanie1967
opened
11 months ago
0
The F/F setup/hold violations are not checked with the correct setup/hold times.
#9
takanie1967
opened
11 months ago
0
Some build fixes
#8
punzik
closed
1 year ago
0
Merged make targets
#7
punzik
closed
1 year ago
3
No format string in sprintf call
#6
punzik
closed
1 year ago
2
Fixed variable declaration in v.h
#5
jjjt-git
closed
1 year ago
0
CVC won't compile on debian bookworm
#4
mole99
closed
1 year ago
5
2 small changes to enable easy build on newer Debian/Ubuntu/Mint distros
#3
jdavid75
closed
5 years ago
0
Set up compatibility fixes
#2
Partmedia
closed
6 years ago
1
fPIC errors
#1
nachiket
opened
7 years ago
14