SPARC: Wrong disassembly of rdy instruction

capstone-engine / capstone

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.

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SPARC: Wrong disassembly of rdy instruction #1450

Open ceeac opened 5 years ago

ceeac commented 5 years ago

Using lastest v4 branch. (commit 2617b1c1)

Steps to reproduce: cstool -d sparc "\x83\x40\x00\x00"
Expected output: rd %y, %g1
Actual output: rd %y, Also, the number of operands is 0 and not 2 as expected.

aquynh commented 5 years ago

will fix in the next major update in v5: https://github.com/aquynh/capstone/issues/1319

rth7680 commented 1 week ago

Still present in v6-alpha.

Rot127 commented 1 week ago

Just checked. This is an issues with flawed generated LLVM tables. This makes the bug not really quickly fixable. Because we would need to generate the decoder tables again. This in turn is a full Auto-Sync update and more work. So it will be part of the Beta when Sparc is updated.