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capstone-engine / capstone

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.
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AArch64 cond operands #1889

Open adamjseitz opened 2 years ago

adamjseitz commented 2 years ago

There are a number of ARM64 instructions that represent a condition code as an operand. These include:

ccmn, ccmp, cinc, cinv, cneg, csel, cset, csetm, csinc, csinv, csneg, fccmp, fccmpe, fcsel

However, capstone does not represent these as an operand:

cstool -d arm64 00bc211e
 0  00 bc 21 1e  fcsel  s0, s0, s1, lt
        ID: 194 (fcsel)
        op_count: 3
                operands[0].type: REG = s0
                operands[0].access: WRITE
                operands[1].type: REG = s0
                operands[1].access: READ
                operands[2].type: REG = s1
                operands[2].access: READ
        Code-condition: 12
        Registers read: nzcv s0 s1
        Registers modified: s0
        Groups: fparmv8

I would suggest adding a new enum value ARM64_OP_COND to arm64_op_type and a field arm64_op_cc cc to the cs_arm64_op structure's value union to more accurately represent these instructions as having four operands.

Rot127 commented 11 months ago

Personally I wouldn't say this is necessary. lt at an operand position is syntactical sugar IMHO. Having condition information at two different places makes the whole design just more complicated.