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capstone-engine / capstone

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.
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Trouble with "msr" instruction (ARM, Capstone 3.0) #235

Closed jabba2989 closed 9 years ago

jabba2989 commented 9 years ago

I'm having problems with disassembling the following 'msr' (thumb2 compiled for ARMv7) instruction: ' 800b93a: f381 8808 msr MSP, r1 '

While iterating through the code capstone stops at this instruction (SKIPDATA Mode = off) like it is unable to decode the instruction. I had no problems with previous versions of capstone and also CEnigma is able to decode the bytecode correctly. So I guess it must be a problem within Capstone Release 3.0 Btw, I'm using the python binding.

Is this a known issue?

aquynh commented 9 years ago

yes, CEnigma is still using v2.x now, hence the difference.

this MSR instructions requires CS_MODE_MCLASS mode.

so rather than initializing with Cs(CS_ARCH_ARM, CS_MODE_THUMB), you should do Cs(CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_MCLASS) instead.

which code are you trying to disassemble?

jabba2989 commented 9 years ago

OK it works now. It's for a code written for the ARM-Cortex-M4F (XMC4500). It totally makes sense why it didn't work. Somehow I overlooked that there is a mode especially for the Cortex-M profil. Thank you for your time and effort.

aquynh commented 9 years ago

it is good to hear that Capstone is useful for you.