Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.
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Wrong operand type for RISCV compressed instruction disassemble #2351
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apach301 opened 1 month ago
Hi,
I tried to disassemble a compressed store instruction, but it turned out that capstone detected wrong operands:
This instruction expected to have two operands: OP_reg and OP_mem. Here is non-compressed analog for store:
Work environment
git clone
, pip