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capstone-engine / capstone

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.
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PowerPC instruction alias slwi and srwi have incorrect 2nd operand in detailed information #2401

Closed joevt closed 3 months ago

joevt commented 4 months ago

Work environment

Questions Answers
OS/arch/bits macOS x86_64
Architecture ppc
Source of Capstone brew --HEAD
Version/git commit HEAD-404912f

Steps to get the wrong result

For slwi:

cstool -d ppc32be 5422E006

For srwi:

cstool -d ppc32be 5466F0BE

Incorrect result

 0  54 22 e0 06  slwi   r2, r1, 0x1c
    ID: 27 (rlwinm)
    Is alias: 2327 (slwi) with ALIAS operand set
    op_count: 3
        operands[0].type: REG = r2
        operands[0].access: WRITE
        operands[1].type: REG = r2
        operands[1].access: WRITE
        operands[2].type: IMM = 0x1c
        operands[2].access: READ

Expected result

The second operand in the operands array should be r1 to match the disassembly and the access type should be READ.

        operands[1].type: REG = r1
        operands[1].access: READ

More info

The information appears to be correct in the real instruction's detailed information.

cstool -d -r ppc32be 5422E006
 0  54 22 e0 06  slwi   r2, r1, 0x1c
    ID: 27 (rlwinm)
    Is alias: 2327 (slwi) with REAL operand set
    op_count: 5
        operands[0].type: REG = r2
        operands[0].access: WRITE
        operands[1].type: REG = r1
        operands[1].access: READ
        operands[2].type: IMM = 0x1c
        operands[2].access: READ
        operands[3].type: IMM = 0x0
        operands[3].access: READ
        operands[4].type: IMM = 0x3
        operands[4].access: READ