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capstone-engine / capstone

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.
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regs_access() for RISC-V yield error #2406

Open KelvinChung2000 opened 2 months ago

KelvinChung2000 commented 2 months ago

Work environment

Questions Answers
OS/arch/bits Pop OS
Architecture x86
Source of Capstone pip
Version/git commit v5.0.1

Expected behavior

regs_access() should return the read and write regs

Actual behavior

Rasing error on unsupported architecture

Steps to reproduce the behavior

from capstone import Cs
from capstone import CS_ARCH_RISCV, CS_MODE_RISCV64

CODE = b"\x83\x3e\x05\x08"
md = Cs(CS_ARCH_RISCV, CS_MODE_RISCV64)
for insn in md.disasm(CODE, 0):
    print(insn.bytes)
    print(f"{insn.mnemonic} {insn.op_str}")
    print(insn.regs_access())

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