Auto-Sync Mips

[wargio]

Your checklist for this pull request

• [x] I've documented or updated the documentation of every API function and struct this PR changes.
• [x] I've added tests that prove my fix is effective or that my feature works (if possible)

Detailed description Adds options for:

• CS_OPT_SYNTAX_NOREGNAME on Mips
• CS_OPT_SYNTAX_NO_DOLLAR (new, removes $ from the register)

Adds support for:

• microMips32r3
• microMips32r6
• nanoMIPS (Generic, NMS1, i7200)
• Mips16
• Mips I ISA
• Mips II ISA
• Mips32 r2 ISA
• Mips32 r3 ISA
• Mips32 r5 ISA
• Mips32 r6 ISA
• Mips III ISA
• Mips IV ISA
• Mips V ISA
• Mips64 r2 ISA
• Mips64 r3 ISA
• Mips64 r5 ISA
• Mips64 r6 ISA
• Octeon (cnMIPS)
• Octeon+ (cnMIPS+)

cstool has been refactored for better UX: now by adding +<feature> you can directly modify the output of capstone using all options.

Arch specific options:
        +att             ATT syntax (only: x86)
        +intel           Intel syntax (only: x86)
        +masm            Intel MASM syntax (only: x86)
        +noregname       Number only registers (only: Arm64, ARM, LoongArch, Mips, PowerPC)
        +moto            Use $ as hex prefix (only: MOS65XX)
        +regalias        Use register aliases, like r9 > sb (only: ARM, Arm64)
        +percentage      Adds % in front of the registers (only: PowerPC)
        +nodollar        Removes $ in front of the registers (only: Mips)
        +nofloat         Disables floating point support (only: Mips)
        +ptr64           Enables 64-bit pointers support (only: Mips)

For example:

$ ./build/cstool -s mipsel64+nofloat "32 C0 38 46 32 02 20 46 32 03 20 "
 0  32 c0 38 46  .byte  0x32, 0xc0, 0x38, 0x46
 4  32 02 20 46  .byte  0x32, 0x02, 0x20, 0x46
$ ./build/cstool -s mipsel64 "32 C0 38 46 32 02 20 46 32 03 20 "
 0  32 c0 38 46  c.eq.d $f24, $f24
 4  32 02 20 46  c.eq.d $fcc2, $f0, $f0

Also fixes the following issues:

• Fix #1519

• Fix #1743

• Fix #1869

• Fix #1990

• Fix #1958

• Fix #2448

  $ ./build/cstool mipsel 0400000c
  0  04 00 00 0c  jal    0x10

• Fix #1054

$ ./build/cstool mips3 0120102d0080e82d40ab500000a0402d0080502d01a0702d40ac1000
 0  01 20 10 2d  move   $v0, $t1
 4  00 80 e8 2d  move   $sp, $a0
 8  40 ab 50 00  dmtc0  $t3, $10, 0
 c  00 a0 40 2d  move   $t0, $a1
10  00 80 50 2d  move   $t2, $a0
14  01 a0 70 2d  move   $t6, $t5
18  40 ac 10 00  dmtc0  $t4, $2, 0

• Fix #1133

  $ ./build/cstool mipsel32r6 b506ff7d
  0  b5 06 ff 7d  pref   0x1f, 0xd($t7)

• Fix #1267

  $ ./build/cstool mips3 00c0502d
  0  00 c0 50 2d  move   $t2, $a2

• Fix #1508

  $ ./build/cstool mips64r2 40021000
  0  40 02 10 00  mfc0   $v0, $2, 0

• Fix #1634

  $ ./build/cstool mips3 46200937
  0  46 20 09 37  c.ule.d        $fcc1, $f1, $f0

• Fix #1673

  $ ./build/cstool mipsel64 03800c4080008c35
  0  03 80 0c 40  mfc0   $t4, $16, 3
  4  80 00 8c 35  ori    $t4, $t4, 0x80

• Fix #1680

  $ ./build/cstool -d mipsel 4000000c0800e003
  0  40 00 00 0c  jal    0x100
      ID: 34 (jal)
      op_count: 1
              operands[0].type: IMM = 0x100
      Groups: call HasStdEnc NotInMicroMips 
  
  4  08 00 e0 03  jr     $ra
      ID: 773 (jr)
      op_count: 1
              operands[0].type: REG = ra
      Groups: return jump HasStdEnc NotMips32r6 NotMips64r6 NotInMicroMips 

• Fix #1780

  # the test in the example is always decoded as xori, i checked also with other disassemblers.
  $ ./build/cstool mips 7c03e83b
  0  7c 03 e8 3b  rdhwr  $v1, $29

• Fix #1851

  $ ./build/cstool mipsel64 "32 C0 38 46 32 02 20 46 32 03 20 46"
  0  32 c0 38 46  c.eq.d $f24, $f24
  4  32 02 20 46  c.eq.d $fcc2, $f0, $f0
  8  32 03 20 46  c.eq.d $fcc3, $f0, $f0

• Fix #1957

  $ ./build/cstool mipsel32r6 "000019f8"
  0  00 00 19 f8  jalrc  $t9

[Rot127]

The auto-sync test is fixed in the modern_testing PR.

[Rot127]

diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/FieldFromInstr.py b/suite/auto-sync/src/autosync/cpptranslator/patches/FieldFromInstr.py
index 67f7faae..58092ea0 100644
--- a/suite/auto-sync/src/autosync/cpptranslator/patches/FieldFromInstr.py
+++ b/suite/auto-sync/src/autosync/cpptranslator/patches/FieldFromInstr.py
@@ -41,9 +41,9 @@ class FieldFromInstr(Patch):

         # Determine width of instruction by the variable name.
         if ffi_first_arg_text[-2:] == "32":
-            inst_width = 4
+            inst_width = b"4"
         elif ffi_first_arg_text[-2:] == "16":
-            inst_width = 2
+            inst_width = b"2"
         else:
             # Get the Val/Inst parameter.
             # Its type determines the instruction width.
diff --git a/.github/workflows/auto-sync.yml b/.github/workflows/auto-sync.yml
index 9d26470d..d1428d06 100644
--- a/.github/workflows/auto-sync.yml
+++ b/.github/workflows/auto-sync.yml
@@ -101,4 +101,3 @@ jobs:
           ./src/autosync/cpptranslator/Differ.py -a ARM --check_saved
           ./src/autosync/cpptranslator/Differ.py -a PPC --check_saved
           ./src/autosync/cpptranslator/Differ.py -a LoongArch --check_saved
-          ./src/autosync/cpptranslator/Differ.py -a Mips --check_saved

[wargio]

@Rot127 fixed

[wargio]

@kabeor

[XVilka]

Would be nice to get it merged, so Coverity would check this code too, also we could update it in Rizin @kabeor