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capstone-engine / capstone

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.
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Problems with access information for some TriCore operands #2526

Open imbillow opened 6 hours ago

imbillow commented 6 hours ago

Originally posted by @Rot127 in https://github.com/capstone-engine/capstone/pull/2523#pullrequestreview-2395323823

Need to fix all fixme in tests/details/tricore.yaml

imbillow commented 6 hours ago

Also note that when an operand of type TRICORE_OP_MEM is written, the access information is wrong.

Maybe need to construct a new Operand Class in the td file to fix this?

Rot127 commented 1 hour ago

Maybe need to construct a new Operand Class in the td file to fix this?

Yeah, this would be the way. Also we would need to mark all store/load instructions with mayLoad = 1 or mayStore = 1. The mapping table generator will add the read/write details for iPtr operands. So making the registers and immediate values of type iPtr might be even enough.