PPC VLE support please

[vanhauser-thc]

Hi,

the PPC support is nice, however in my projects the code is always in variable length encoding, which does not seem to be supported in capstone (all modes fail for VLE bytecode). I would appreciate support for it :)

[aquynh]

can you give some inputs (in hexcode format) and the outputs (assembly) taken from your code?

thanks

[rpw]

VLE binaries are common for Freescale MCUs, which are widely used in the automotive sector. VLE for PowerPC is like Thumb for ARM [1]. Upstream (LLVM) does not suppport VLE at the moment. Here's a thread of someone attempting to add support for VLE in LLVM July 2014:

http://lists.llvm.org/pipermail/llvm-dev/2014-July/074613.html

VLE output looks like this:

FLASH:00026330 00 80                       se_mflr   r0
FLASH:00026332 18 21 06 F0                 e_stwu    r1, -0x10(r1)
FLASH:00026336 D5 01                       se_stw    r0, 0x14(r1)
FLASH:00026338 79 FF AF 09                 e_bl      loc_21240
FLASH:0002633C C5 01                       se_lwz    r0, 0x14(r1)
FLASH:0002633E 00 D3                       se_extsb  r3
FLASH:00026340 00 90                       se_mtlr   r0
FLASH:00026342 20 F1                       se_addi   r1, 0x10
FLASH:00026344 00 04                       se_blr

[1] Variable-Length Encoding (VLE) Extension Programming Interface Manual http://cache.freescale.com/files/soft_dev_tools/doc/support_info/VLEPIM.pdf?fsrch=1

[vanhauser-thc]

thanks ralph for already replying :) it is not just freescale, and not just automotive though

code example:

2D 07                             se_bmaski r7, 0x10
70 D8 E3 FE                       e_lis     r6, -0x3C02
70 0B 02 F0                       e_li      r0, 0x5AF0
6D C3                             se_slwi   r3, 0x1C
44 30                             se_or     r0, r3
1C C6 C0 00                       e_add16i  r6, r6, -0x4000
D1 06                             se_stw    r0, 4(r6)
7C E0 02 78                       xor       r0, r7, r0
D1 06                             se_stw    r0, 4(r6)
C0 06                             se_lwz    r0, 0(r6)
66 40                             se_btsti  r0, 4
E2 FE                             se_bne    0xFFFFC8D0
00 04                             se_blr

And some good links: http://www.st.com/st-web-ui/static/active/en/resource/technical/document/user_manual/CD00161395.pdf http://application-notes.digchip.com/314/314-68105.pdf

[wargio]

I've added VLE support on r2, how can this be achieved on cs? https://github.com/radare/radare2/pull/7899

[aquynh]

Can you list all instructions you added here (would be nice with sample input)?

[wargio]

i can do something better: https://github.com/radare/radare2/blob/master/libr/asm/arch/ppc/libvle/vle.c#L171 https://github.com/radare/radare2/blob/master/libr/asm/arch/ppc/libvle/vle.c#L281 for samples, i have this: https://github.com/wargio/libvle/blob/master/test.c I have to update it, since the latest version is the one modified for r2.

give me a few minutes to update it.

[wargio]

pushed.

[aquynh]

can you please make a pull req?

[wargio]

I didn't clone capstone and modified it. I don't even know where to begin

[aquynh]

What do you mean? I suppose you are familiar with Github?

[wargio]

yes, but not with capstone. Mine is a handwritten decoder for vle, not a patch for capstone, that's why i can't make a PR

[lancelot2112]

What's needed to add VLE support? It's not apparent how we can contribute given most of the disassembly information is in autogenerated files. Where's the information to generate said files? What additional information would you need for PowerPC vle? Do you need the attached Instruction Set Architecture PDFs translated to a specific format to feed the autogenerator? I'd also assume we'd need to modify the interpreter to be able to handle switching between 2 and 4 byte instructions.

[lancelot2112]

1230 seems to have it figured out, will maybe start there and see what I can do. No promises.