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capstone-engine / capstone

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.
http://www.capstone-engine.org
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Support for RISC-V instruction disassembly #966

Open deepsrc opened 7 years ago

deepsrc commented 7 years ago

This issue will track the changes required to support the disassembly of RISC-V (www.riscv.org) instruction set. I will start with the support for RV64 first and then add the support for RV32 and compressed instruction sets.

aquynh commented 7 years ago

cool, do you mean you want to contribute new arch in Risc-V support?

deepsrc commented 7 years ago

Yes, thats right

aquynh commented 7 years ago

awesome, keep me updated!

blanham commented 7 years ago

RV32 disassembly was just merged, it might make sense to start with it and then move to RV64 once it's merged.

octopus-io commented 7 years ago

hi, you say RV32 disassembly was just merged, but i cannot find this merge anywhere :/ otherwise it will be awesome to have RV32/64 supported.

fevv9 commented 6 years ago

There is other merge of RISC-V RV32 to capstone from March 2018: https://github.com/benhorgan/capstone/tree/master/arch/riscv Check also https://github.com/aquynh/capstone/pull/1131 from https://github.com/porto703/capstone/tree/riscv

ultrasoc commented 5 years ago

The Risc-v port moved to: https://github.com/ultrasoc/capstone/tree/master/arch/riscv Not sure what is involved in contributing this back?

XVilka commented 4 years ago

@ultrasoc can you please send a pull request?

testhound commented 4 years ago

Can someone tell me what the status of the RISC-V port is? I see it is on the next branch.

iamlouk commented 3 years ago

Ping! :D Any news? I would really like to use this. Should i use @ultrasoc 's fork or what can be found in the next branch of this repository? Is RSIC-V support usable?

Thank you all contributing very much for your work!

nylon7 commented 2 years ago

Ping! :D Is RSIC-V support usable?

Thank you all contributing

iamlouk commented 2 years ago

I have been using the RISC-V implementation that can be found in the next branch for a while now and it works quite well. I have used it on rv64gc binaries without any major problems.

I needed some workarounds for working with the detail part of Instructions though! Some decisions that were made there I personally find inconvenient. The contents of the detail struct (e.g. operands) are encoded like you would if using pseudo-instructions. By that I mean that for example jr reg is encoded as an jalr instruction (fine so far), but with only that one operand instead of the actual three operands x0, reg, $0. Another weirdness is that both, jal r0, <whatever> and jal r1, <whatever> translate to an RISCV_INS_JAL with op_count 1 and the only operand being the <whatever> immediate (Can still be disambiguated using the mnemonic).

But all in all for what I am doing it works just fine!

nylon7 commented 2 years ago

If I want to contribute, can I make changes based on that branch?