This PR cherry-picks the changes from a different PR by @edubart.
The central idea is the elimination of the ROM we used to build the device tree.
This is now built directly by the emulator, into a new memory range we call DTB.
The new memory range appears right before RAM and, at 1MiB, will enable more complex initialization of the Cartesi Machine.
This PR cherry-picks the changes from a different PR by @edubart. The central idea is the elimination of the ROM we used to build the device tree. This is now built directly by the emulator, into a new memory range we call DTB. The new memory range appears right before RAM and, at 1MiB, will enable more complex initialization of the Cartesi Machine.
Depends on https://github.com/cartesi/grpc-interfaces/pull/23 and https://github.com/cartesi/machine-emulator-defines/pull/8.