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cascode-labs / morpheus

Generate Maestro circuit test benches in Cadence Virtuoso
MIT License
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Update Plan region spacing in schematic creation #6

Closed Jetsama closed 3 months ago

Jetsama commented 1 year ago

"Plan" step in schematic creation doesn't space the regions of terminals correctly. Update to be based on the max between the DUT size and max size of region.

Jetsama commented 3 months ago

This was fixed to use DUT bounding box and max region size: image image