rebind does not work with RiscV ISA

cdonovick / peak

Peak : Processor Specification Language ala Newell and Bell's ISP

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rebind does not work with RiscV ISA #202

Closed rdaly525 closed 4 years ago

rdaly525 commented 4 years ago

Looks like it is due to subclassing a custom ADT

branch:rebind-riscv tests/test_risc.py:155

cdonovick commented 4 years ago

This pretty fundamental to how rebind / ADT works. I could reformulate the ISA to avoid inheritance but that would effect any code @phanrahan has written for the assembler