This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, and test it on FPGA.
Interrupts can simply be implemented as a function call.
Whenever the interrupt signal is asserted, we fetch the ISR as the next instruction for the pipeline. There is no need to stall the pipeline or re-execute instructions.
When doing this, we need to make sure that the standard conventions for invoking function calls are followed (meaning that certain registers need to be preserved, return address needs to be recorded, etc.)
Interrupts can simply be implemented as a function call.
Whenever the interrupt signal is asserted, we fetch the ISR as the next instruction for the pipeline. There is no need to stall the pipeline or re-execute instructions.
When doing this, we need to make sure that the standard conventions for invoking function calls are followed (meaning that certain registers need to be preserved, return address needs to be recorded, etc.)