Changed uart to use a single external fifobus interface

[gcc42]

The uartlite module has been modified to use a single external fifobus interface, while still using different RX fifo and TX fifo internally.

[cfelton]

Some of the examples have not been updated? The example regression tests are failing

cd examples
py.test

[gcc42]

Yeah, I somehow missed them on local . Have to manage syncing the fifo interfaces there too. Will update the PR in a few hours.

[gcc42]

Errors have been fixed in the board examples by mapping one UART FIFOBus interface with 2 in the 'command_bridge'(Travis CI build is timing out again for some reason, not so on my local machine). Later, as you said earlier, one of two things would have to be done:

1. Change all the module external interfaces to use just one FIFOBus, not two, or
2. Provide the stopgap with the module in the FIFOBus.assign_read_write_path()

Just wanted to put that out there.

[gcc42]

Added Google doc format docstrings to the UART and the sphinx docs.

[gcc42]

Wrote the assign_rw func in fifobus(you were right about DRY) and cleaned up the docstrings. Also did the mods you suggested in sphinx docs, but IMO the sphinx docs need some more cleanup and linking, so will do that separately.

[cfelton]

@forumulator docs in a separate pull-request sounds good. Note, I have been working on the sphinx-docs in the cso branch.