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cfelton / rhea

A collection of MyHDL cores and tools for complex digital circuit design
MIT License
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"Fixed Conversion Error" #28

Closed Vikram9866 closed 7 years ago

Vikram9866 commented 8 years ago

varables v and f are used without defining them as Signal. It causes problem during conversion.

cfelton commented 8 years ago

@Vikram9866 in general the use of "variables" is not an issue. The changes you made are not needed. The use of variables is convertible and synthesizable and this FIFO has been used on numerous hardware platforms.

Can you provide more information on the error you are encountering?

Vikram9866 commented 8 years ago

myhdl.ConversionError: in file Fifo.py, line 91: Type mismatch with earlier assignment: v

cfelton commented 8 years ago

@Vikram9866 which version of myhdl are you using?

Vikram9866 commented 8 years ago

@cfelton Iam using this package myhdl-1.0dev-py2.7

cfelton commented 8 years ago

@Vikram9866 this needs more investigation, this is a new conversion error with 1.0dev. Let me investigate when I have a little more time and when I have access to a computer to verify this is a new conversion error in 1.0 that did not exist in 0.9.

In the future having the complete information in the PR will help the process and save us all a little time :)

cfelton commented 8 years ago

@Vikram9866 I was wrong, the module failed to convert with 0.9.1 as well. I have pushed a commit that resolves the issue using variables (not signals) and added a conversion test.

I forgot that most of my modules use fifo_fast (which is a sync fifo) instead of fifo_sync, I will need to do some more investigation to determine when/how/why fifo_sync broke (or maybe it was always broke).

Thanks for pointing out this issue.

cfelton commented 7 years ago

This was fixed via another method in the base.