Added addtional port mappings to Digilent Anvyl board

[NickShaffner]

Hey Chris, working more with the Digilent Anvyl and thought I'd push the changes I've got upstream. These have all been tested on real hardware. Intending to get the rest of it in, but have some questions about specifying tristate signals in rhea's port maps.

[cfelton]

@NickShaffner defining tristates isn't something that I have tackled yet. I believe the most straightforward would be to have a port attribute tristate, when defining a port simply add tristate=True.

    'sda': dict(pin=14, tristate=True)

There will need to be some updates to the add_port function.

[cfelton]

Looks like it is already supported, just need to test and document:

'sda': dict(pin=14, sigtype=SignalTristate(bool(0)))

The tristate=True option is more user-friendly, will see if it is not too difficult to add.

[NickShaffner]

@cfelton

Looks like it is already supported, just need to test and document

Nice!

[NickShaffner]

@cfelton

A simple way to specify intbv vs modbv could also be useful - so the size could automatically be inferred.

[NickShaffner]

@cfelton

Hey Chris, hopefully not hassling you too much here, but have a newbie-esque question here.

In rhea, for bidirectional blocks of IO like 'wings' or 'pmod' connectors, I notice some of the boards (like the papilio recently) define all the signals together such that they get aggregated into an intbv (I think), ex:

'wingC': dict(pins=(91, 92, 94, 95, 98, 2, 3, 4, 5, 9, 10, 11, 12, 15, 16, 17), iostandard=VCCO),

The thing is, many times, you want some of these component signals as inputs and some as outputs. Specifying Tristate for this guy would only allow the whole thing to be an input or an output. Of course there are shadow signals, but I don't think there is a way to selectively write and read individual bits of the same signal in myhdl, (is there?) Grouping is still very useful though - is there a way to specify that each bit should be independent from the other and in an array of signals rather than in a single intbv?

[coveralls]

Coverage decreased (-0.02%) to 70.876% when pulling 8edc192108790a5fdc051ddb5f988be69b04dc6a on NickShaffner:master into 0fe37d161b960e683d59b85269618c3e6658df3e on cfelton:master.

[coveralls]

Coverage decreased (-0.01%) to 70.876% when pulling 8edc192108790a5fdc051ddb5f988be69b04dc6a on NickShaffner:master into 0fe37d161b960e683d59b85269618c3e6658df3e on cfelton:master.

[cfelton]

@NickShaffner Things like wingC are not really "ports", as you stated. They are expansion connectors but they are useful in the base class to capture the portless pins.

What you want to do is use the add_port_name or define a custom board definition for your configuration.

Example: 
        brd.add_port_name('led', 'wingC', 7)

where wingC is a 16-bit port bit-vector

To extract a range from the port, the slice class has to be used, example:

            brd.add_port_name('msb', 'wingC', slice(16,8))