Additional port definitions for Digilent Anvyl

cfelton / rhea

A collection of MyHDL cores and tools for complex digital circuit design

MIT License

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Additional port definitions for Digilent Anvyl #33

Closed NickShaffner closed 7 years ago

NickShaffner commented 7 years ago

A few things (as noted inline) eventually need to be declared as tri-state as previously discussed.

Also was curious for any feedback on the handling of the overlapping ports: expansion <-> [jd, je, jf, jg]

coveralls commented 7 years ago

Coverage remained the same at 70.955% when pulling 114a34c8b91f99f523efb4d352abd78e4c982341 on NickShaffner:master into d753943f738ec0e258d904328fc97582a81aa625 on cfelton:master.