Initial support for Diligent CModA7 (15T + 35T), Expanded Zybo Definition, Fix Vivado building on windows, Fixed VHDL conversion via rhea.build.toolflow.convert, added Clock.ticks property

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Coverage remained the same at 70.364% when pulling 558a84fdf316a5fc39d4e411283cbe1eb9c88303 on NickShaffner:master into aae5e3f469f829f26f97387718d23a6d2c4315c1 on cfelton:master.

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Coverage increased (+0.003%) to 70.367% when pulling 3fc7dd516f44fa8d53dba87f88884c07e43138b1 on NickShaffner:master into aae5e3f469f829f26f97387718d23a6d2c4315c1 on cfelton:master.

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Coverage decreased (-0.02%) to 70.34% when pulling 239a23e4af55d5a3fb7fb128023ccd0140d8ad90 on NickShaffner:master into aae5e3f469f829f26f97387718d23a6d2c4315c1 on cfelton:master.

[NickShaffner]

@cfelton I'm a bit confused as to why Clock.gen() can override hticks via a passed in parameter - ignoring the frequency and period. I see several of the tests seem to make use of this, but I don't understand why? It seems to me that the 'official' and only way to set hticks should be through the Clock() constructor. either via the frequency parameter, or perhaps an alternate optional hticks parameter that computes frequency. Would you be amiable to me doing such a refactoring?

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Coverage decreased (-0.01%) to 70.353% when pulling a14556346e94751387862b66e82f2ef94961483e on NickShaffner:master into aae5e3f469f829f26f97387718d23a6d2c4315c1 on cfelton:master.

[coveralls]

Coverage decreased (-0.01%) to 70.353% when pulling a14556346e94751387862b66e82f2ef94961483e on NickShaffner:master into aae5e3f469f829f26f97387718d23a6d2c4315c1 on cfelton:master.

[cfelton]

I'm a bit confused as to why Clock.gen() can override hticks via a passed in parameter - ignoring the frequency and period.

In myhdl the simulation step is not tied to an absolute timescale (well there is in some cases, like trace signals). To determine what the tick/htick should be either need all the possibly clocks (to set them relative to each other), know that absolute time you want sim step to represent, or let the user set it.

In the code the absolute (1) and user (3) are currently supported but the absolute is currently tied to 1ns the user (modifying hticks) lets the user override this - cases where frequency greater than 500 MHz is desired.

When the user sets the htick, it doesn't change the frequency of the clock but rather the absolute time unit that a simulation step will represent.

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Coverage increased (+0.02%) to 70.38% when pulling f27ca14ea4d4e53a7bf0829842ea6fbacc17d7b8 on NickShaffner:master into aae5e3f469f829f26f97387718d23a6d2c4315c1 on cfelton:master.

[NickShaffner]

Sorry this pull request keeps going :) I suppose I need to figure out how to create separate pull requests in github.

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Coverage decreased (-0.03%) to 70.332% when pulling e9506bfad8168560cfabd04bc0f11cedd570e2d2 on NickShaffner:master into aae5e3f469f829f26f97387718d23a6d2c4315c1 on cfelton:master.

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Coverage decreased (-0.06%) to 70.305% when pulling 40e78257e9a14b29759bab05120b32d678443e2f on NickShaffner:master into aae5e3f469f829f26f97387718d23a6d2c4315c1 on cfelton:master.

[cfelton]

Because the build tools are not tested by travis-ci (FPGA tools not available) I will have to pull from your branch to my local computer and tests the FPGA board builds. Some of the Vivado build changes I don't understand, I want to make sure they work with multiple versions etc.

This might take me a couple days because I have MyHDL GSoC items I need to finish in this week.

[NickShaffner]

@cfelton No problem or rush, and sorry that things are confusing. I've just been fixing things as I go along to get my basic flow working.

The changes were related to:

• Quoting strings so that pathnames with spaces in them are handled correctly instead of being interpreted as two arguments
• Escaping backslashes for vivido TCL, so that backslashes in windows paths (or elsewhere) are interpreted correctly.
• subprocess needs the full name of the executable to call. Previously it was calling 'vivado' which works under unix, but not windows. Under windows it needs to call 'vivado.bat'.

These changes would likely also benefit the other toolflows as well, but I only have vivado installed, so can only test it there.

I'll make the changes you requested and submit another changelist later today.

[coveralls]

Coverage decreased (-0.06%) to 70.305% when pulling e70f413d8b933552b1216aaa4f2e0892554ddc03 on NickShaffner:master into aae5e3f469f829f26f97387718d23a6d2c4315c1 on cfelton:master.

[NickShaffner]

Apologies for cramming so much stuff into this one pull request. In future, I'll separate changes into branches so they are more topical.

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Coverage increased (+0.01%) to 70.379% when pulling 081ff00981cc36a55ef43b9daa89e9d8bbefc669 on NickShaffner:master into aae5e3f469f829f26f97387718d23a6d2c4315c1 on cfelton:master.

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Coverage increased (+0.004%) to 70.369% when pulling c4b226098ffdb681a715348a170d3236d979d790 on NickShaffner:master into aae5e3f469f829f26f97387718d23a6d2c4315c1 on cfelton:master.

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Coverage increased (+0.01%) to 70.379% when pulling 00b304eca413ca06f8f82881ff4d3c7d006e9c65 on NickShaffner:master into aae5e3f469f829f26f97387718d23a6d2c4315c1 on cfelton:master.

[coveralls]

Coverage increased (+0.01%) to 70.379% when pulling 00b304eca413ca06f8f82881ff4d3c7d006e9c65 on NickShaffner:master into aae5e3f469f829f26f97387718d23a6d2c4315c1 on cfelton:master.