Removing debug prints from xilinx clock management pll calculations.

cfelton / rhea

A collection of MyHDL cores and tools for complex digital circuit design

MIT License

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Removing debug prints from xilinx clock management pll calculations. #48

Closed NickShaffner closed 7 years ago

NickShaffner commented 7 years ago

Err, not sure why my previous commits are coming through in this one? Only a couple of lines in the one file changed though.

coveralls commented 7 years ago

Coverage increased (+0.02%) to 70.4% when pulling f077f5d0f2e200ba180b73eac05efa5989608827 on NickShaffner:master into 9223b1d366ff579858a3203751aaa3d5a9fb7596 on cfelton:master.

cfelton commented 7 years ago

yeah I don't understand why all the commits are coming through as well.