Open hstarmans opened 7 years ago
@hstarmans yes the SDRAM controller in rhea is not complete - I must have made a mistake merging some of it in to the main branch (should only be available as WIP on the sdram branch)? It is essentially a port of @udara28's version but using some of the framework in rhea.
Abstract Conversion is not possible sdram_sdr_controller is not finished
Dear all,
I am trying to test the rhea sdram controller on the xula2-lx25. I have already done a successful test with the sdram controller of @udara28, see sdram controlller, who was coached in a Google Summer code 2015 by @devbisme. The sdram interface of udara is similar to the sdram interface of @cfelton see here; both are based upon xesscorp. I am, however, unable to get a conversion with rhea.
The code fails AttributeError: 'SDRAMInterface' object has no attribute 'lock'.
In sdram_sdr_controller: line 60: sdram.lock but SDRAMInterface does not have this attribute line 81: In line 81 of sdram_sdr_controller, the following default portmap is defined; 'extmem': SDRAMInterface(clock)
However; SDRAMInterface does not accept clock.
Furthermore, in Rhea's SDRAMInterface, the functions loadmode and precharge are not present. Rhea does seem to have a placeholder for them in the dictionary "Commands"; LMR and PRE, i.e. Load Mode Register and Precharge. Rhea also defines two types of writes; controller side and a side identified as . The functions _read and _write are slightly different from read and write in Udara's work.
Conclusion Conversion is not possible sdram_sdr_controller is not finished