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cfelton / rhea

A collection of MyHDL cores and tools for complex digital circuit design
MIT License
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spi_slave_fifo_async #59

Open mngr0 opened 5 years ago

mngr0 commented 5 years ago

Abstract: Use fifo_async instead of fifo_sync in spi slave

Hi,

I am trying to edit spi_slave_fifo to sli_slave_fyfo_async, since I think that I need different clocks in read and write. I have made a try, and in simulation it works, but it doesn't work on the real board.

I am quite new in FPGA development, so baybe I just made a naive mistake... Or maybe I have to re-check things since I am synthesising with a different tool.

Can you please give a look? Or give me a hint where the problem may be

here is a link to the main module https://github.com/mngr0/rhea/blob/development/test/test_cores/test_spi/spi_slave_pulsegen.py

and here is a link to spi_slave_fifo_async https://github.com/mngr0/rhea/blob/development/rhea/cores/spi/spi_slave_fifo_async.py

run "make test-pulse" to test and generate wave file

Background project: I am working on a FULLY open source project, so I am using icestorm (arachne-pnr and yosys) to program a Lattice ICE40. The project is about controlling a stepper motor given commanded position via SPI