UART lite modifications

[cfelton]

The following clean-up needs to be done to the UART module.

1. Change the fifo port interface to use a single fifobus. The write side of the FIFOBus will write to the TX fifo and the read side of the fifobus will read from the RX fifo. Internally the TX read and RX write will be accessed via another FIFOBus interface.
2. Update the doc strings to use the Google doc format.
3. Add documentation to the sphinx docs, bare minimum include the autodocs of the uartlite module.
4. Make sure the code is PEP8.

[gcc42]

1. Done, although this need to be done for other modules too.
2. Doc Strings updated.
3. Sphinx Docs added
4. The code is already mostly PEP 8