cfoge / VHDL_parse

A collection of Python scripts to make working with VHDL easier
MIT License
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Multiple generics in entity not working? #2

Closed svenka3 closed 3 months ago

svenka3 commented 1 year ago

I tried to parse a LIFO from a public repo and I see generics not gettings parsed correctly.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity lifo is
    generic (
        g_INDEX_WIDTH : positive := 2; -- internal index bit width affecting the LIFO capacity
        g_DATA_WIDTH  : positive := 8 -- bit width of stored data
    );
    port (
        i_clk : in std_ulogic; -- clock signal
        i_rst : in std_ulogic; -- reset signal

        i_we   : in  std_ulogic; -- write enable (push)
        i_data : in  std_ulogic_vector(g_DATA_WIDTH - 1 downto 0); -- written data
        o_full : out std_ulogic; -- full LIFO indicator

        i_re    : in  std_ulogic; -- read enable (pop)
        o_data  : out std_ulogic_vector(g_DATA_WIDTH - 1 downto 0); -- read data
        o_empty : out std_ulogic -- empty LIFO indicator
    );
end entity lifo;

Can you please take a look?

cfoge commented 3 months ago

sure, thanks for the heads up

cfoge commented 3 months ago

should be fixed now