PTP/1588 and PHY

[changtimwu]

ordinary clock master and ordinary slave can be done in this way. http://www.st.com/st-web-ui/static/active/en/resource/technical/document/application_note/DM00030825.pdf

[changtimwu]

1548P

Ingress

• Insert TS-tag after SA.
• TS-tag could be 10-byte long.
• Droping or sending unmodified packet to CPU/MAC.

Egress

• Remove the TS-tag
• Fill the correction field
• Update the original TS

Others

• two time Stamping queues
  • Stamp HI
  • Stamp Low

[changtimwu]

• The port facing OC master is TC slave
• The port facing OC slave is TC master

[changtimwu]

page 269 PTP memory. Each register is 32-bit wide

@ptpreg_read = ( phy_no, ptpreg)->
  p = (port for port in devinfo().ports when port.phy_no is phy_no)[0]
  org_page = set_page( p, PHYPAGE_PTP)
  sw.smi_register_write p.phy_if, p.phy_id, PTPREG_ADREAD, ptpreg
  datalo = sw.smi_register_read(p.phy_if, p.phy_id, PTPREG_DATA_LO).value
  datahi = sw.smi_register_read(p.phy_if, p.phy_id, PTPREG_DATA_HI).value 
  sw.smi_register_write p.phy_if, p.phy_id, 0x16, org_page
  datahi<<16 | datalo

@ptpreg_write = ( phy_no, ptpreg, ptpval)->
  p = (port for port in devinfo().ports when port.phy_no is phy_no)[0]
  org_page = set_page( p, PHYPAGE_PTP)
  sw.smi_register_write p.phy_if, p.phy_id, PTPREG_ADWRITE, ptpreg
  sw.smi_register_write p.phy_if, p.phy_id, PTPREG_DATA_LO, ptpval & 0xffff
  sw.smi_register_write p.phy_if, p.phy_id, PTPREG_DATA_HI, ptpval >> 16
  sw.smi_register_write p.phy_if, p.phy_id, 0x16, org_page
  null

[changtimwu]

marvell phy pin bootstrap configuration

共有4根config pin, CONFIG[3:0], 每根PIN 藉由接到不同LED 就代表 4bit得值 所以共有 4*16 = 64 個 bool 值可調整,

CONFIG[1] 可以當 PTPinput, 被拿來當PTP使用時, CONFIG[1] 就自動失去4bit值得決定能力 CONFIG[2] 可以當 PTPclock, 被拿來當PTP使用時 CONFIG[4] 就自動失去4bit值得決定能力 CONFIG[0] & CONFIG[3] 跟 PTP 無關, PTP透過 software 調成enable or disable, 都不會影響他, 所以PTP_EN 那欄 always 秀 X

[changtimwu]

For one-step PTP, the messages Sync, pdelay_req, Delay_req need to insert the time stamp into PTP-frame by hardware.

[changtimwu]

MV-S107695-00_88E1548P_Datasheet_20150325.pdf

Page 52

• 有分 MAC interface & Media Interface, 想像他們是成對的, 雖然 phy address 是獨立的, 但仍會相互影響 意思就是 當 Media interface link 到 1000BaseT 時, MAC interface 就會在1000 Mbps
• 可以用 register 17_1(page 1 register 71) bit 5 & 10, 查 SGMII 是否 link & sync
• 如果 SGMII 的 AN 沒開, bit 5 & 10 意思一樣, 如果AN有開, bit 10 代表是否 AN 成功建立 link.

[changtimwu]

需要P4R27b{0,1} register 來對跳?

[changtimwu]

yes, set P4R27 to 0x7f83 is the solution. What a pity you didn't insist trying it.