STM32

[changtimwu]

for cortex m3(ex. f107), specify the core speed as 72 instead of 168 http://armcortexm.blogs.upv.es/stm32f4-discovery-and-printf-redirection-to-debug-viewer-in-keil/ Add the following code to make printf work

#include <stdio.h>
#include "main.h"

int fputc(int ch, FILE *f)
{
  ITM_SendChar(ch); 
  return ch;
}

[changtimwu]

SPI flash schematics of stm3210c http://www.st.com/st-web-ui/static/active/en/resource/technical/document/user_manual/CD00212441.pdf

reference doc http://wenku.baidu.com/view/bccdaa5c804d2b160b4ec0ec?fr=prin

[changtimwu]

SD signal	N-KEY	3210C
card detect	PD2	PE0
chip select	PA4	PA4
MISO	PC11	PC11
MOSI	PC12	PC12
SCLK	PC10	PC10

[changtimwu]

disable optimization(-O0) to debug

hanging at SD_GoIdleState() https://my.st.com/public/STe2ecommunities/mcu/Lists/STM32Java/Flat.aspx?RootFolder=https%3a%2f%2fmy%2est%2ecom%2fpublic%2fSTe2ecommunities%2fmcu%2fLists%2fSTM32Java%2fSD%20card%20with%20fatfs%20on%20STM3210C-EVAL&FolderCTID=0x01200200770978C69A1141439FE559EB459D758000F9A0E3A95BA69146A17C2E80209ADC21&currentviews=169

That guy clive1 is right. It works with a 2GB SD card.

[changtimwu]

http://www.openedv.com/posts/list/37.htm Someone has released SPI+SD block addressing on STM32. Porting it to to mach cube's HAL or SPL api.

[changtimwu]

locked in ETH_GetSoftwareResetStatus () == SET https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=https%3a%2f%2fmy%2est%2ecom%2fpublic%2fSTe2ecommunities%2fmcu%2fLists%2fcortex_mx_stm32%2fStm32F2%20%20Ethernet%20start%20up%20infinite%20Loop&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B&currentviews=2230

The problematic code block.

/*---------------------------------  DMA  ------------------------------------*/
/**
  * @brief  Resets all MAC subsystem internal registers and logic.
  * @param  None
  * @retval None
  */
void ETH_SoftwareReset(void)
{
  /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
  /* After reset all the registers holds their respective reset values */
  ETH->DMABMR |= ETH_DMABMR_SR;
}

/**
  * @brief  Checks whether the ETHERNET software reset bit is set or not.
  * @param  None
  * @retval The new state of DMA Bus Mode register SR bit (SET or RESET).
  */
FlagStatus ETH_GetSoftwareResetStatus(void)
{
  FlagStatus bitstatus = RESET;
  if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
  {
    bitstatus = SET;
  }
  else
  {
    bitstatus = RESET;
  }
  return bitstatus;
}

related defines

#define ETH_DMABMR_SR        ((uint32_t)0x00000001)  /* Software reset */

related document 29.8.4 DMA register description

The issue summarized in one sentence. _When we did a reset to the ethernet's DMA, it's never completed.

Got Answer!!: The link MII_TXCLK <-> PC3 has been disconnected for some unknown reason.

[changtimwu]

f107 reference manual here http://www.st.com/web/en/resource/technical/document/reference_manual/CD00171190.pdf

[changtimwu]

16 pin MII signals

• MDC - PC1
• MDIO - PA2
• RXDV - PA7
• RXD0 - PC4
• RXD1 - PC5
• RXD2 - PB0
• RXD3 - PB1
• RX_ER - PB10
• TXD3 - PB8
• TXEN - PB11
• TXD0 - PB12
• TXD1 - PB13
• TXD2 - PC2
• TXCLK - PC3
• CRS - PA0
• COL - PA3

unknown related PIN

• RXC - PA1

PTP pins

• PPS - PB5 (mis-connected to mode2)

[changtimwu]

原本接在PB5 的 mode 2 請改接到沒使用的PB9 PB5 要拿來當作 1588 PPS pin PB5 要當 mode 2 請記得去調整 AFIO_MAPR, 把PTP_PPS bit set as 0

[changtimwu]

some ETH not remap reference http://www.oryx-embedded.com/doc/stm32f107__eth_8c_source.html

mii example http://andybrown.me.uk/2012/09/01/ethernet-phy-stm32f107/

another PHY http://www.farnell.com/datasheets/1700434.pdf

[changtimwu]

DIP switch

• mode0 -> PB15
• mode1 -> PB14
• mode2 -> PB5

button

• start -> PA6

LED

• FINISH1 <- PC6
• FINISH0 <- PC7
• STS1 <- PC8
• STS0 <- PC9

[changtimwu]

ST's 2009 old code. Its SPL is 3.1.2. 智嵌's code is almost identical to this.
http://www.st.com/web/en/catalog/tools/PF257862#

Let's check the JUMPER. See anything different between 3210C in MII mode and NKEY.

[changtimwu]

check if input 25Mhz clock is on PA1(RX_CLK) & PC3(TX_CLK) .

[changtimwu]

Realtek PHY http://www.100y.com.tw/pdf_file/80-REALTEK-RTL8201CL.pdf

[changtimwu]

KEIL install

• MDK516.EXE
• KEIL_Lic.exe
• stsw-link009.zip
• STMF1 Device family pack
• copy flash alogrithm copy C:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\1.1.0\Flash\STM32F10x_CL.FLM into C:\Keil_v5\ARM\flash

[changtimwu]

RX works but TX doesn't work. It's because LocalTime not get increased and TX jobs(ex. ARP timer) are all based on the value of LocalTime.

LocalTime -> Time_Update() -> SysTick_Handler()

SysTick_Handler() is ISR...and why it's not triggered??

TX fails and on the switch side you can spot CRC errors.

every octet seems OR with 0x44 . ex

0xff | 0x44 -> 0xff 0x00 | 0x44 -> 0x44 0x01 | 0x44 -> 0x45